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Assembly Hall of Shame: Racing to CPU performance bottom

A competitive leaderboard ranks x86 instructions by slowest single-instruction latency, led by fxrstor64 at 198 billion cycles.

7 items485 engagement113 comments Hacker NewsLobstersRedditPress

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Summary, timeline and people extracted by Claude from 7 items across 4 sources · 21h ago. Quotes are verbatim.

The Assembly Hall of Shame is a GitHub project that inverts typical CPU optimization by measuring the worst-case latency of single x86 instructions rather than the fastest. The current champion is fxrstor64 on AMD Ryzen 7 5800H, achieving 198,002,498,236 cycles by exploiting PCIe fabric contention and memory hierarchy delays; the project includes a leaderboard of 27+ instructions ranked by slowest execution time.

  • The Assembly Hall of Shame inverts conventional CPU optimization by measuring worst-case single-instruction latency rather than best-case performance.
  • The current champion is fxrstor64 on AMD Ryzen 7 5800H, achieving 198 billion cycles through PCIe fabric contention and memory hierarchy exploitation.
  • The project maintains a leaderboard of 27+ x86 instructions ranked by slowest execution time, from nop at 1 cycle to fxrstor64 at 198 billion cycles.
  • The project circulated across multiple developer communities (Hacker News, Lobsters, Reddit) between August 7-9, 2026.

How it unfolded

  1. Report Posted to Reddit

    The project appears on Reddit with title 'Assembly Hall of Shame: Racing to the bottom of CPU performance,' continuing circulation across developer communities.

  2. Report Shared on Lobsters

    The same project is posted to Lobsters community, receiving 56 points and 2 comments, spreading awareness among systems-focused developers.

  3. Report Project published to Hacker News

    Assembly Hall of Shame GitHub repository gains visibility on Hacker News with 419 points and 109 comments, presenting a leaderboard of x86 instructions ranked by slowest single-instruction latency.

What people are saying verbatim

“Instruction latency analysis usually focuses on performance optimization—making code run as fast as possible. The Assembly Hall of Shame takes the opposite approach: searching for the absolute floor of single-instruction performance.”

Assembly Hall of Shame project · GitHub repository · Aug 6

“Use fxrstor64 to load 512-byte FPU/MMX/XMM state from a high-latency MMIO region in the PCIe fabric, then starve the fabric while the load is in flight — a fleet of hammer cores pounds a different high-latency MMIO register with tight 4-byte reads, saturating the PCIe root complex and endpoint with non-posted transactions”

Assembly Hall of Shame project · GitHub repository · Aug 6

Voices from the web unedited

  • This is such a pathetically weak take that it is barely even worth a response. Yes, chip manufacturers make features for their products, powerful features which can be misused. Shock, and horror.

    globalafr/programming18h agoview on r/programming ↗

  • Ok, if this is an issue we should care about, then I wonder why the chip manufacturers engineering teams did allow it to make it into the final design, and people still bought the chips?

    Grouchy-Trade-7250r/programming18h agoview on r/programming ↗

  • Im just asking what the significance of this topic is. The git doesn't answer that, it's just a list. and you didn't either.

    Grouchy-Trade-7250r/programming18h agoview on r/programming ↗